#ifndef PLAT_H
#define PLAT_H

#define PLAT_MEM_BASE 0x50000000
#define PLAT_MEM_SIZE 0x8000000

#define PLAT_STACK_SIZE 0x4000      /* stack for each CPU */

#define PLAT_NR_CPUS                4
#define PLAT_CLUSTER_COUNT          1
#define PLAT_CORE_COUNT             (PLAT_NR_CPUS * PLAT_CLUSTER_COUNT)

#define UART_IRQ_ID 33

#define GICD_BASE   (0x8000000ULL)
#define GICR_BASE   (0x80A0000ULL)
#define UART_BASE   (0x9000000ULL)

#define REPORT_CRASH    1       /* dump register and memory in case of exception */

#endif
